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| Tuesday, 3 October 2017 |

Here is an informal description of a trivial algorithm A: all nodes stop immediately and output "1".

Your task is to formalise this algorithm, using the state machine formalism of Section 4.3. Be precise, be careful. Define all components: Input_A, States_A, Output_A, init_A,d, send_A,d, and receive_A,d.

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