The topic for the seminar presentation is "Building Blocks for Analog Computing memory circuits"
Given below are the topics for the individual seminar presentation:
1. ADC / DAC implementation - 19.05.2021, 12:15 - Dipesh Monga
2. Analog Activation Circuits (For ex. ReLU)- 26.05.2021, 12:15 - Omar Numan
3. Capacitive and resistive based Vector Matrix Multiplier- 02.06.2021, 12:15 -Waqas Siddiqui
4. Capacitive Memory storage based computing circuits- 02.06.2021, 13:15 - Kazybek Adam
How to do this course:
- Based on the topic, 5 latest papers are supposed to be selected for preparing the seminar.
participant has to present a 45-minute presentation which will be delivered using a zoom session.
At the end of each seminar, the presenter will assign homework for the others based on the seminar. The assignment should be submitted to the presenter's email. Deadlines to submit the assignment can be checked in the Assignments section.
**These topics are assigned on a first come first serve basis. To select your topic you need to comment/reply on your name and title of the topic on the post entitled "TOPIC SELECTION" in general discussion.
***Suggested conferences/journals: papers and tutorials from ISSCC-2020/2021, JSSC, TCAS etc.
Here are some recent studies on the topics relevant to seminar topics and some suggested conferences/journals: papers and tutorials from ISSCC-2020/2021, JSSC, TCAS etc are preffered.
1. S. Xie, C. Ni, A. Sayal, P. Jain, F. Hamzaoglu and J. P. Kulkarni, "16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 248-250, doi: 10.1109/ISSCC42613.2021.9365932.
2. J. -W. Su et al., "16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 250-252, doi: 10.1109/ISSCC42613.2021.9365984.
3. Y. -D. Chih et al., "16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 252-254, doi: 10.1109/ISSCC42613.2021.9365766.
4. X. Si et al., "15.5 A 28nm 64Kb 6T SRAM Computing-in-Memory Macro with 8b MAC Operation for AI Edge Chips," 2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, pp. 246-248, doi: 10.1109/ISSCC19947.2020.9062995.
5. H. Jia et al., "15.1 A Programmable Neural-Network Inference Accelerator Based on Scalable In-Memory Computing," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 236-238, doi: 10.1109/ISSCC42613.2021.9365788.
6. Z. Chen, X. Chen and J. Gu, "15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 240-242, doi: 10.1109/ISSCC42613.2021.9366045.
7. R. Khaddam-Aljameh, P. -A. Francese, L. Benini and E. Eleftheriou, "An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 2, pp. 372-385, Feb. 2021, doi: 10.1109/TVLSI.2020.3037871.
Assignment 1: Return it to Dipesh Monga (firstname.lastname@example.org) before 26th May, 2021 (Deadline over)
Assignment 2: Return it to Omar Numan (email@example.com) before 2nd June, 2021 (Deadline over)
Assignment 3: Return it to Waqas Siddiqui (firstname.lastname@example.org) before 16th June, 2021 (Deadline over)
Assignment 4: Return it to Kazybek Adam (email@example.com) before 16th June, 2021 (Deadline over)