The project topics cover analog IC design including generic circuits for high frequencies, RF/UW transceiver block design, and digital design including VHDL programming.
Topics will be assigned to the students by 1.3 2022 .
Before this, please take a look on the available topics in the list below, and consider what are your own interests. You are free to choose any topic but in case of shared interest to a certain topic, I have to make a decision.
Choose three topics and send your choices in order of preference to firstname.lastname@example.org.
You will thereafter be informed of your topic on Tuesday 1.3. 2022
Topic: Design of reconfigurable switched capacitor power convertorInstructor: Dipesh Monga (email@example.com, room MT8 2191)
DC-DC converters are widely used in residential, commercial, and industrial applications, such as renewable energy conversion systems, electric traction devices, and, mainly, power supplies. The student designs a basic reconfigurable switched capacitor power convertor with multiple charge gain. Knowledge of Analog IC design flow is a plus.
Topic: Design of Current-starved capacitance-controlled ring oscillatorInstructor: Dipesh Monga (firstname.lastname@example.org, room MT8 2191)
The student designs a ring oscillator in a 65nm CMOS process utilizing a predefined architecure. The student analyzes the architecture and makes minor adaptations based on given specifications. Knowledge of Analog IC design flow is a plus.
Topic: N-bit Thermometer Coded Vernier Delay LineInstructor: Tze Hin Cheung (Dicky) (email@example.com, room MT8 2186)
In this topic the student implements a Vernier Delay Line which acts as a Time-to-Digital Converter. In addition to implementing the delay line, the student also characterizes the performance through theory and simulator.
Topic: A fractional 2/3 frequency dividerInstructor: Tze Hin Cheung (Dicky) (firstname.lastname@example.org, room MT8 2186)
In this topic the student implements a known divide by 2/3 frequency divider operating at above 10 GHz. The student has to characterize the proper sizes for the transistor for the desired operating frequency while maintaining wide frequency operation range and low power consumption. The tasks include schematic level simulations of the design in Cadence Virtuoso and evaluation of the fractional division operation.
Topic: A 24-40GHz Down Conversion MixerInstructor: Saeed Naghavi (email@example.com, room MT8 2190)
In this project, the basic structure of an mm-Wave Gilbert Cell mixer will be studied and then a modified version of that (based on a reference paper) will be compared to the conventional one. Through this project, you will practice how different stages of the mixer (input stage, switching quad, and load stage) will affect the gain, noise, and linearity trade-offs.
Topic: Performance analysis of RF/mm-Wave switchesInstructor: Saeed Naghavi (firstname.lastname@example.org, room MT8 2190)
RF switches are key building blocks for RF/mm-Wave front end ICs. The insertion loss of a switch is often the most critical parameter. Switch designers would make every effort to minimize insertion loss while providing enough isolation, power handling, and linearity. These parameters will be studied in this project and the performance of a few switches (2-3 reference papers) will be compared to each other.
Topic: Design of high-linearity sampling switchInstructor: Santeri Porrasmaa (email@example.com, room MT8 2190)
In order to enable state-of-the-art performance in data converters for current and next generation communications, the sampling front-end of a data converter needs to be designed to yield sufficient performance while leaving some safety margin. A critical building block in realizing high-performance sampling front-ends is the sample and hold circuit (S/H). In this project, the student designs a bootstrapped switch and compares it's performance to a simple MOS-C sampler.
Topic: Bootstrapped track-and-hold circuitInstructor: Miikka Tenhunen (firstname.lastname@example.org, room MT8 2190)
Sampling circuits are required in most analog-to-digital converters to keep the analog input constant during conversion. In this topic, a sampling switch is implemented that saves analog voltage values to a capacitor according to a given clock signal. The switch is bootstrapped to enhance linearity. Tools are developed that allow frequency domain performance evaluation of the simulated layout.
Topic: Capacitive digital-to-analog converterInstructor: Miikka Tenhunen (email@example.com, room MT8 2190)
Digital-to-analog converters (DAC) are often used in control circuitry and as parts of analog-to-digital converters. The task is to design a (non-sampling) capacitive DAC, i.e. a DAC constructed out of binary weighted capacitors. The goal is to keep the area manageable while achieving good conversion accuracy. Tools are developed that allow static and dynamic performance evaluation of the simulated layout.
Topic: Design and development of 8 channels interface between micro-controller and ADCsInstructor: Muhammad Tanweer (firstname.lastname@example.org, room MT8 2191)
Interface type can be I2C, SPI or both. Sampling frequency is 2 kHz with 24 bit ADCs. Each channel uses dedicated ADC.
Topic: Design of energy efficiency data receiver based on near field communication to organize and archive the received data.Instructor: Muhammad Tanweer (email@example.com, room MT8 2191)
Topic: Design of a small analog vector-matrix multiplier (VMM) with MDACInstructor: Numan Omar (firstname.lastname@example.org, room MT8 2191)
The student will design first a multiplying digital to analog converter (MDAC), and use the MDAC to build, e.g., 8x8 VMM and analyze its performance.
Topic: Design of analog activation functions for neural networksInstructor: Numan Omar (email@example.com, room MT8 2191)
The student will design some analog activation functions like ReLU, tanh, sigmoid, etc., and analyze their performance.
Topic: RiscV implementation with Cadence's GPDGInstructor: Andrei Spelman (firstname.lastname@example.org, Room MT8 2189)
RiscV implementation with Cadence's GPDG (Used in Digital Microelectronics 2 and 3). Code is ready, place and routing is needed. Student will familiarize (him/her)self with source code and generate and optimize layout based on it.
Topic: Cummings FIFOInstructor: Andrei Spelman (email@example.com, Room MT8 2189)
Student will design Cummings FIFO (asynchronous First In First Out buffer). Preferably, this project is implemented using Chisel3 but VHDL is possible as well. Choice can positively affect the grade. Ideally, student will design FIFO with Chisel, testbench with Python and run place and routing. I understand that doing all steps listed above will be challenging in terms of one course and we can discuss about the goals of the project.
Topic: Design of math functions using power efficient opamsInstructor: Kazybek Adam (firstname.lastname@example.org, room MT8 2191)
In this project the goal is to build a top-level black box circuit which implements few mathematical functions such as addition, subtraction, multiplication, etc. using custom-designed low-power opamps.Such math operations can be used in implementing machine learning algorithms in chip-level and having them consume little power is essential. Students are free to use their previously designed opamps and optimize them for low power consumption or to explore other opamp variants. One example can be inverter based opamps.
Topic: Bit-Serialising in a 16-bit microprocessor for power savingInstructor: Gaurav Singh (email@example.com, room MT8 2191)
For energy-harvesting based sensor-node, we have to dynamically scale the power requirement of various blocks on the SoC. This bit-serialization will use the same requirement to switch between parallel/serial ALU processing using techniques like clock-gating and power-gating. This would help to save some power dynamically if required at an expense of some additional area.