Syllabus

LEARNING OUTCOMES

Is familiar with the VHDL-hardware description language and the digital design implementation flow (synthesis tools) from VHDL to layout. Is familiar with the functionality of microcontrollers and basics of programming with assembly language.

Credits: 5

Schedule: 27.02.2023 - 29.05.2023

Teacher in charge (valid for whole curriculum period):

Teacher in charge (applies in this implementation): Marko Kosunen

Contact information for the course (applies in this implementation):

CEFR level (valid for whole curriculum period):

Language of instruction and studies (applies in this implementation):

Teaching language: English. Languages of study attainment: English

CONTENT, ASSESSMENT AND WORKLOAD

Content

• valid for whole curriculum period:

  Six coding exercises that teach the elementary structures of VHDL and simulation methods. Self -guided design project about VHDL description of a microcontroller and its synthesis with digital synthesis and place-and-route-tools.

Assessment Methods and Criteria

• valid for whole curriculum period:

  Accepted VHDL-coding exercises and study diary of the design project.

Workload

• valid for whole curriculum period:

  Introductory lectures (2h, 2 times)

  VHDL-coding exercises (2h, 6 times)

   

  Six coding exercises that teach the elementary structures of VHDL and simulation methods. Self -guided design project about VHDL description of a microcontroller and its synthesis with digital synthesis and place-and-route-tools.

DETAILS

Substitutes for Courses

• valid for whole curriculum period:

  Substitutes for Courses

Prerequisites

• valid for whole curriculum period:

  Prerequisites

FURTHER INFORMATION

Further Information

• valid for whole curriculum period:

  Teaching Language : English

  Teaching Period : 2022-2023 Spring IV - V
  2023-2024 Spring IV - V

  Enrollment :

  Registration for Courses on Sisu (sisu.aalto.fi).

Description