The project topics cover analog IC design including generic circuits for high frequencies, RF/UW transceiver block design, and digital design including VHDL programming.
Topics will be assigned to the students in the first meeting on 26.2.2019.
Before this, please take a look on the available topics in the list below, and consider what are your own interests. You are free to choose any topic but in case of shared interest to a certain topic, we have to negotiate.
Topic: Design and development of 16 channels interface between micro-controller and ADCsInstructor: Muhammad Tanweer (email@example.com, room 2191)
Interface type can be I2C, SPI or both. Sampling frequency is 2 kHz with 24 bit ADCs. Each channel uses dedicated ADC.
Topic: Design and development of Mechanomyography (MMG) platformInstructor: Muhammad Tanweer (firstname.lastname@example.org, room 2191)
Study and comparison of MMG methods and development of a single channel MMG front end hardware platform using off the shelf electronic components.
Topic: Pulse-Shrinking Delay Line Time-to-Digital ConverterInstructor: Okko Järvinen (email@example.com, room 2190)
The student builds an ideal model of a pulse-shrinking delay line time-to-digital converter (TDC), and uses the model to analyze and understand the parameters involved in the pulse-shrinking. The key elements of the circuit are then replaced by transistor-level circuits, and the circuit performance is simulated and reported.
Topic: Digital Delay-Locked LoopInstructor: Okko Järvinen (firstname.lastname@example.org, room 2190)
The student designs a digital delay-locked loop (DLL / ADDLL) first as an ideal model, followed by transistor-level implementation of said model. The functionality and performance of the system is then confirmed with circuit simulations, and the results are reported.
Topic: Digital back-end for near-field communication (NFC) transceiver.Instructor: Ilia Kempi (email@example.com, Room 2190)
This work consists of developing digital building blocks for a transceiver back-end. Depending on the skill of the student, the work can include from one to several of the following elements: FM0 decoder, PWM encoder, flow control state machine, error correction mechanism. The result should be a system-level VHDL description which is synthesizable for clock speds of MHz range. It is expected that the student is comfortable with sequential circuits and system design.
Topic: Pipelined CORDIC algorithm for real-time DSP applicationsInstructor: Ilia Kempi (firstname.lastname@example.org, Room 2190)
The purpose of this work is to produce a scalable pipelined VHDL description of the CORDIC algorithm. The performance of the implemented system must be thoroughly evaluated by co-simulations with an ideal Matlab model. Depending on the skill of the student, the design could be expanded to perform various computations on complex numbers. It is mandatory to be familiar with Matlab.
Topic: Low power CMOS crystal oscillatorInstructor: Tuomas Haapala (email@example.com, room 2193)
The student designs a microwatt 100-kHz crystal oscillator in a generic 45-nm CMOS process utilizing a predefined architecure. The student analyzes the architecture and makes minor adaptations based on given specifications. In addition, the student examines crystal modeling and creates a simulation model based on a given crystal datasheet.
Topic: Low-Power Low-Dropout Regulator and reference Design for SoC-applicationsInstructor: Andreas Hammer ( firstname.lastname@example.org, room 2190)
A Low-Dropout Regulator (LDO) is an efficient way to provide clean supply voltage for sensitive analog (or digital) devices such as time-based analog-to-digital converters. Ideally an LDO would be seen as an ideal voltage source for the load device, capable of feeding infinite current, but due to it's own supply and manufacturing limitations, the design must be carried out to match the load requirements. A typical LDO operates on resistive negative feedback referenced to a voltage at the error operational amplifier input. In this project, the student should be able to minimize the dropout voltage (DC input vs output) and aim for the lowest possible output voltage that is able to drive a 1mA load current. The performance of the opamp is crucial to LDO operation and thus the student should start by using an ideal opamp model in his/her design. In addition, the student should become familiar with generating the reference's for the LDO with either a Betamultiplier- or a bandgap reference circuit.
Topic: Low-Power RF-to-digital communication interfaceInstructor: Andreas Hammer (email@example.com, room 2190)
Communication with an RFID chip can be performed by modulating the carrier wave with various techniques. Pulse-interval-encoding (PIE) is a method to encode the data to the carrier wave with modulating the carrier wave amplitude as a short pulse. The information is coded in the time between these pulses and this time interval is then detected by a digital counter. In this project the student will design a pulse (envelope) detection circuit that extracts the modulated amplitude data from the carrier wave. On top of the PIE information, the student should design a simple circuit to extract the carrier wave frequency as a clock signal for the digital circuit to use. During this project the student learns the design techniques for a low-power comparator and an inverter chain.
Topic: Digitally-controlled delay line operated between 1-2 GHz with adjustable resolution.Instructor: Mahwish Zahra (firstname.lastname@example.org, room 2186)
In this project, student will explore basic design aspects of LO generation for multi-antenna receivers. The delay line will be designed in cadence environment with functional verification through eldo simulations. The project covers different aspects related to design of individual delay units and how different design parameters affect their delays.
Topic: Multi-phase LO generation between 1-2 GHz from reference clock signalInstructor: Mahwish Zahra (email@example.com, room 2186)
Generate multi-phase signals from reference LO clock, including 4-phase generation for mixers and pulse-skipping operation for multi-antenna receivers. Design will be carried out in cadence environment with functional verification through eldo simulations. The student will gain insight about some well-established techniques for multi-phase generation as well as experiment with simple circuit blocks for enabling pulse skipping operation.
Topic: Balun LNAInstructor: Kalle Spoof (firstname.lastname@example.org, room 2190)
In this work, the student implements a noise-cancelling balun LNA based on an existing architecture. The LNA provides wideband input mathcing and single-ended to differential conversion while providing good noise and linearity performance. The performance is verified and optimized with simulations.
Topic: Beam-steering and N-path filtersInstructor: Kalle Spoof (email@example.com, room 2190)
Beam-steering enables electrical control of transmission/reception direction. N-path filters can create tunable band-pass filters. This project combines these two concepts to achieve simultaneous tunable spatial and frequency filtering into one block, which can be used as the first stage of a receiver.
Topic: Switched capacitor power amplifier (SCPA) - House of Cards topologyInstructor: Ali Saleem (firstname.lastname@example.org, room 2189)
The scaling of power amplifier voltage and power by digital circuitry have been the main topic for few years. However, the demand of high voltage RF waveforms using low voltage thin oxide transistors paved its way in SCPA e.g., 5 V RF waveforms using 1 V transistors. Therefore, the task is to study and analyze a topology of SCPA.
Topic: Performance analysis of transmitter RF-front endInstructor: Ali Saleem (email@example.com, room 2189)
In this assignment, you are going to study the effects of non-linearity in a integrated radio frequency front end. In particular, You are going to work on power amplifier topology. Since the power amplifiers are one the most important block where such non-linearities merge together, hence, degrading the transmitter performance.
Topic: Low Noise Amplifier for Bluetooth applicationsInstructor: Muhammad Annus (firstname.lastname@example.org, room 2191)
Low Noise Amplifiers are 1st block in receiver chain. Their performance is very crucial for further signal processing in receiver. You will design a common gate topology LNA for Bluetooth applications and simulate both pre-layout and post-layout simulations and analyze its performance in 65nm technology.
Topic: Voltage Controlled OscillatorInstructor: Muhammad Annus (email@example.com, room 2191)
Voltage Controlled Oscillators are key components in frequency synthesizers and are the most power-hungry blocks. In this project you will design 3 VCOs and perform layout of one of the VCOs and compare their performance for Bluetooth applications in 65nm technology.
Topic: Design of an E-band power amplifierInstructor: Md Najmussadat (firstname.lastname@example.org, room 2191)
The demand for high data rate communication systems is growing rapidly and the millimeter -wave spectrum, with a broad frequency range available for high capacity wireless communication, is drawing increasing attention . In the future communication systems, it is of key importance that the transceivers are capable of operating in multiple frequency bands and with complex signals. High frequency bands are used for satellite communication, automotive radar, point-to-point communication as well as imaging and radar applications. Due to long distances of these applications and high atmospheric losses at these frequency bands, power amplifiers with high output power are required for link budget , making the power amplifier’s design one of the major challenges in the design of the mm-wave transceiver.
Topic: Design of an E-band Doherty power amplifierInstructor: Md Najmussadat (email@example.com, room 2191)
Modern communication systems employ different modulation techniques that exhibit high peak-to-average power ratios (PAPRs) to achieve high data rates and high spectral efficiency. Doherty power amplifier provides high power added efficiency (PAE) at peak as well as back-off power level.
Topic: 60 GHz Broadband Low-Noise AmplifierInstructor: Raju Ahamed (firstname.lastname@example.org, room 2191)
Low noise amplifier (LNA) is a critical building block in wireless receivers. Since LNA is the first block in the receiver path, the gain and noise figure from the LNA determines the noise figure of the whole receiver. In this project you will design a 60 GHz LNA. As the demand for high data rate communication system is increasing rapidly, we need large available bandwidth. Frequencies around 60 GHz are very attractive due to widely unlicensed spectrum around 60GHz that can support high data rate wireless communication. Therefore, your target is to design a 60GHz broadband LNA.
Topic: 60 GHz Wideband SPDT SwitchInstructor: Raju Ahamed (email@example.com, room 2191)
In many applications single-pole double-through (SPDT) switches are often used so that both the transmitter and receiver can share the same antenna. Using a single antenna for both the transmitter and receiver increases integration which reduces the cost of the system. In this project you will design a SPDT switch. As the demand for high data rate communication system is increasing rapidly, we need large available bandwidth. Frequencies around 60 GHz are very attractive due to widely unlicensed spectrum around 60GHz that can support high data rate wireless communication. Therefore, your target is to design a 60GHz broadband SPDT switch.