Osion kuvaus

  • Materials

    Here are some recent studies on the topics relevant to seminar topics and some suggested conferences/journals: papers and tutorials from ISSCC-2020/2021, and 2021/2022, JSSC, TCAS, etc are preferred.

    • References for Topic 1:

    • - Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R. et al. Memory devices and applications for in-memory computing. Nat. Nanotechnol. 15, 529–544 (2020). https://doi.org/10.1038/s41565-020-0655-z (general article)
      - Krestinskaya, O., Choubey, B. & James, A.P. Memristive GAN in Analog. Sci Rep 10, 5838 (2020). https://doi.org/10.1038/s41598-020-62676-7
      - O. Krestinskaya, K. N. Salama and A. P. James, "Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits," in IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 2, pp. 719-732, Feb. 2019, doi: 10.1109/TCSI.2018.2866510.
      - T. -H. Hsu et al., "A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731675.
      - J. -O. Seo, M. Seok and S. Cho, "ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 258-260, doi: 10.1109/ISSCC42614.2022.9731654.
      - W. -S. Khwa et al., "A 40-nm, 2M-Cell, 8b-Precision, Hybrid SLC-MLC PCM Computing-in-Memory Macro with 20.5 - 65.0TOPS/W for Tiny-Al Edge Devices," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731670.
      - J. -M. Hung et al., "An 8-Mb DC-Current-Free Binary-to-8b Precision ReRAM Nonvolatile Computing-in-Memory Macro using Time-Space-Readout with 1286.4-21.6TOPS/W for Edge-AI Devices," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731715.
      - M. Chang et al., "A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731679.
      - S. D. Spetalnick et al., "A 40nm 64kb 26.56TOPS/W 2.37Mb/mm2RRAM Binary/Compute-in-Memory Macro with 4.23x Improvement in Density and >75% Use of Sensing Dynamic Range," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731725.
      - Z. Chen, X. Chen and J. Gu, "15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 240-242, doi: 10.1109/ISSCC42613.2021.9366045.

    • References for Topic 2:

    • - Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R. et al. Memory devices and applications for in-memory computing. Nat. Nanotechnol. 15, 529–544 (2020). https://doi.org/10.1038/s41565-020-0655-z (general article)
      - M. E. Sinangil et al., "A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS," in IEEE Journal of Solid-State Circuits, vol. 56, no. 1, pp. 188-198, Jan. 2021, doi: 10.1109/JSSC.2020.3031290.
      - R. Khaddam-Aljameh, P. -A. Francese, L. Benini and E. Eleftheriou, "An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 29, no. 2, pp. 372-385, Feb. 2021, doi: 10.1109/TVLSI.2020.3037871.
      - K. Ueyoshi et al., "DIANA: An End-to-End Energy-Efficient Digital and ANAlog Hybrid Neural Network SoC," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731716.
      - S. Xie, C. Ni, A. Sayal, P. Jain, F. Hamzaoglu and J. P. Kulkarni, "16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 248-250, doi: 10.1109/ISSCC42613.2021.9365932.
      - J. -W. Su et al., "16.3 A 28nm 384kb 6T-SRAM Computation-in-Memory Macro with 8b Precision for AI Edge Chips," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 250-252, doi: 10.1109/ISSCC42613.2021.9365984.
      - H. Zhu et al., "COMB-MCM: Computing-on-Memory-Boundary NN Processor with Bipolar Bitwise Sparsity Optimization for Scalable Multi-Chiplet-Module Edge Machine Learning," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731657.
      - H. -W. Hu et al., "A 512Gb In-Memory-Computing 3D-NAND Flash Supporting Similar-Vector-Matching Operations on Edge-AI Devices," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 138-140, doi: 10.1109/ISSCC42614.2022.9731775.
      - D. Wang, C. -T. Lin, G. K. Chen, P. Knag, R. K. Krishnamurthy and M. Seok, "DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 266-268, doi: 10.1109/ISSCC42614.2022.9731659.

    • References for Topic 3:

    • - Y. Lecun, L. Bottou, Y. Bengio and P. Haffner, "Gradient-based learning applied to document recognition," in Proceedings of the IEEE, vol. 86, no. 11, pp. 2278-2324, Nov. 1998, doi: 10.1109/5.726791. (LeNet)
      - Alex Krizhevsky, Ilya Sutskever, Geoffrey E. Hinton, "ImageNet Classification with Deep Convolutional Neural Networks", Part of Advances in Neural Information Processing Systems 25 (NIPS 2012). URL (ImageNet)
      - Zhao, Bo & Feng, Jiashi & Wu, Xiao & Yan, Shuicheng. (2017). A survey on deep learning-based fine-grained object classification and semantic segmentation. International Journal of Automation and Computing. 14. 10.1007/s11633-017-1053-3. (Check AlexNet part)
      - Simonyan, Karen, and Andrew Zisserman. "Very deep convolutional networks for large-scale image recognition." arXiv preprint arXiv:1409.1556 (2014). (VGG-16)
      - L. Fick, S. Skrzyniarz, M. Parikh, M. B. Henry and D. Fick, "Analog Matrix Processor for Edge AI Real-Time Video Analytics," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 260-262, doi: 10.1109/ISSCC42614.2022.9731773. (Figure 15.8.5)

    • References for Topic 4:

    • - Szegedy, Christian, et al. "Going deeper with convolutions." Proceedings of the IEEE conference on computer vision and pattern recognition. 2015. (GoogLeNet)
      - Zhao, Bo & Feng, Jiashi & Wu, Xiao & Yan, Shuicheng. (2017). A survey on deep learning-based fine-grained object classification and semantic segmentation. International Journal of Automation and Computing. 14. 10.1007/s11633-017-1053-3. (Check GoogLeNet part)
      - He, Kaiming, et al. "Deep residual learning for image recognition." Proceedings of the IEEE conference on computer vision and pattern recognition. 2016. (ResNet)
      - Huang, Gao, et al. "Densely connected convolutional networks." Proceedings of the IEEE conference on computer vision and pattern recognition. 2017. (DenseNet)

    • References for Topic 5:

    • - Sebastian, A., Le Gallo, M., Khaddam-Aljameh, R. et al. Memory devices and applications for in-memory computing. Nat. Nanotechnol. 15, 529–544 (2020). https://doi.org/10.1038/s41565-020-0655-z
      - T. -H. Hsu et al., "A 0.8V Intelligent Vision Sensor with Tiny Convolutional Neural Network and Programmable Weights Using Mixed-Mode Processing-in-Sensor Technique for Image Classification," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731675. (Vision sensor)
      - M. Chang et al., "A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731679. (Figure 16.3.1.)
      - D. Im et al., "DSPU: A 281.6mW Real-Time Depth Signal Processing Unit for Deep Learning-Based Dense RGB-D Data Acquisition with Depth Fusion and 3D Bounding Box Extraction in Mobile Platforms," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 510-512, doi: 10.1109/ISSCC42614.2022.9731699. (Signal processing unit)

    • References for Topic 6:

    • - Medina-Santiago A, Hernández-Gracidas CA, Morales-Rosales LA, Algredo-Badillo I, Amador García M, Orozco Torres JA. CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions. Sensors. 2021; 21(21):7071. https://doi.org/10.3390/s21217071 (Figures 3, 4, 7).
      - S. Ashok Kumar, J. Charles Pravin. (2021) Performance Evaluation of Sub 5 nm GAA NWMBCFET using Silicon Carbide Source/Drain Material. IETE Journal of Research 0:0, pages 1-6. (Figure 3).
      - S. Xing and C. Wu, "Implementation of A Neuron Using Sigmoid Activation Function with CMOS," 2020 IEEE 5th International Conference on Integrated Circuits and Microsystems (ICICM), 2020, pp. 201-204, doi: 10.1109/ICICM50929.2020.9292239. (Sigmoid).
      - Krestinskaya, Olga & Choubey, B. & James, A.. (2020). Memristive GAN in Analog. Scientific Reports. 10. 10.1038/s41598-020-62676-7. (Figure 2, reLU, leaky, relu, hard tanh).
      - J. -O. Seo, M. Seok and S. Cho, "ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 258-260, doi: 10.1109/ISSCC42614.2022.9731654. 
      - S. Lee et al., "A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 1-3, doi: 10.1109/ISSCC42614.2022.9731711. (Figure 11.1.5.)

    • References for Topic 7:

    • - J. -O. Seo, M. Seok and S. Cho, "ARCHON: A 332.7TOPS/W 5b Variation-Tolerant Analog CNN Processor Featuring Analog Neuronal Computation Unit and Analog Memory," 2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, pp. 258-260, doi: 10.1109/ISSCC42614.2022.9731654. (read about AMEM)
      - Z. Chen, X. Chen and J. Gu, "15.3 A 65nm 3T Dynamic Analog RAM-Based Computing-in-Memory Macro and CNN Accelerator with Retention Enhancement, Adaptive Analog Sparsity and 44TOPS/W System Energy Efficiency," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 240-242, doi: 10.1109/ISSCC42613.2021.9366045. (Figure 15.3.1.)
      -S. Xie, C. Ni, A. Sayal, P. Jain, F. Hamzaoglu and J. P. Kulkarni, "16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 248-250, doi: 10.1109/ISSCC42613.2021.9365932. (eDRAM cell)

    • References for Topic 8:

    • - Medina-Santiago A, Hernández-Gracidas CA, Morales-Rosales LA, Algredo-Badillo I, Amador García M, Orozco Torres JA. CMOS Implementation of ANNs Based on Analog Optimization of N-Dimensional Objective Functions. Sensors. 2021; 21(21):7071. https://doi.org/10.3390/s21217071 (Figures 3, 4, 7. summing/inverting amplifier).
      - Y. -D. Chih et al., "16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 252-254, doi: 10.1109/ISSCC42613.2021.9365766. (Figure 16.4.3. Digital adder)
      - D. Bankman, L. Yang, B. Moons, M. Verhelst and B. Murmann, "An Always-On 3.8 $\mu$ J/86% CIFAR-10 Mixed-Signal Binary CNN Processor With All Memory on Chip in 28-nm CMOS," in IEEE Journal of Solid-State Circuits, vol. 54, no. 1, pp. 158-172, Jan. 2019, doi: 10.1109/JSSC.2018.2869150. (analog addition)

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