Topic outline

  • Seminar Topics

    The seminar topics are:

    Topic 1: Sources of nonidealities and compensating techniques in resistive-based in-memory computing neural network accelerators.

    Presenter: Omar Numan

    Refs:

    • S. Jain, A. Sengupta, K. Roy, and A. Raghunathan, “RxNN: A Framework for Evaluating Deep Neural Networks on Resistive Crossbars,” IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 40, no. 2, pp. 326–338, Feb. 2021.
    • T. P. Xiao, C. H. Bennett, B. Feinberg, S. Agarwal, and M. J. Marinella, “Analog architectures for neural network acceleration based on non-volatile memory,” Applied Physics Reviews, vol. 7, no. 3, p. 031301, Sep. 2020. 
    • Y. Jeong, M. A. Zidan, and W. D. Lu, “Parasitic Effect Analysis in Memristor-Array-Based Neuromorphic Systems,” IEEE Trans. Nanotechnology, vol. 17, no. 1, pp. 184–193, Jan. 2018.
    • S. Agarwal, R. L. Schiek, and M. J. Marinella, “Compensating for Parasitic Voltage Drops in Resistive Memory Arrays,” in 2017 IEEE International Memory Workshop (IMW), Monterey, CA, USA: IEEE, May 2017.
    • Z. He, J. Lin, R. Ewetz, J.-S. Yuan, and D. Fan, “Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network Mapping,” in Proceedings of the 56th Annual Design Automation Conference 2019, Las Vegas NV USA: ACM, Jun. 2019.
    • B. Feinberg, S. Wang, and E. Ipek, “Making Memristive Neural Network Accelerators Reliable,” in 2018 IEEE International Symposium on High Performance Computer Architecture (HPCA), Vienna: IEEE, Feb. 2018.


    Topic 2:      Neuromorphic computer architectures

    Presenter: Aleksi Korsman

    Refs:

    • F. Akopyan, et al., D. S. (2015). TrueNorth: Design and tool flow of a 65 MW 1 million neuron programmable neurosynaptic chip. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 34(10), 1537–1557.

    • M. Davies, et al. (2018). Loihi: A neuromorphic manycore processor with on-chip learning. IEEE Micro, 38(1), 82–99.

    • Abdallah, A. B., & Dang, K. N. (n.d.). Neuromorphic computing principles and organization. SpringerLink.


    Topic 3:      Energy efficient implementation of Probabilistic circuits.

    Presenter: Jelin Leslin

    Description: A probabilistic circuit is a type of probabilistic model. Probabilistic models are mathematical models that represent uncertainty or randomness in a data/system using probability distributions. A probabilistic circuit's probability distribution is represented using a circuit structure so it can be efficiently evaluated using standard computer hardware.

    Refs:

    • Shah, Nimish, et al. "Problp: A framework for low-precision probabilistic inference." Proceedings of the 56th Annual Design Automation Conference 2019. 2019.
    • Shah, Nimish, et al. "Acceleration of probabilistic reasoning through custom processor architecture." 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE). IEEE, 2020.
    • Olascoaga, Laura I. Galindez, et al. "On hardware-aware probabilistic frameworks for resource constrained embedded applications." 2019 Fifth Workshop on Energy Efficient Machine Learning and Cognitive Computing-NeurIPS Edition (EMC2-NIPS). IEEE, 2019.
    • Shah, Nimish, et al. "9.4 piu: A 248gops/w stream-based processor for irregular probabilistic inference networks using precision-scalable posit arithmetic in 28nm." 2021 IEEE International Solid-State Circuits Conference (ISSCC). Vol. 64. IEEE, 2021.


    Topic 4:     Efficient Probabilistic Circuits Inference in Hardware

    Presenter: Lingyun Yao

    Refs:

    • Sommer, L., Weber, L., Kumm, M., & Koch, A. (2020). Comparison of arithmetic number formats for inference in sum-product networks on fpgas. 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM).

    • París, I., & Díez, F. J. (2020). Sum-product networks: A survey. arXiv. https://doi.org/https://arxiv.org/abs/2004.01167v1
    • YooJung Choi, Antonio Vergari and Guy Van den Broeck. Probabilistic Circuits: A Unifying Framework for Tractable Probabilistic Models, In , 2020.
    • Saadat, H., Bokhari, H., & Parameswaran, S. (2018). Minimally biased multipliers for approximate integer and floating-point multiplication. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 37(11), 2623–2635.

    Topic 5: Time-Domain Neural Network

    Presenter: Ahmed Mohey

    Refs:

    • D. Miyashita, S. Kousai, T. Suzukiand J. Deguchi, “A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing”, IEEE Journal of Solid-State Circuits, vol. 52, no. 10, pp. 2679–2689, 2017, doi: 10.1109/jssc.2017.2712626.
    • Y. Toyama, K. Yoshioka, K. Ban, S. Maya, A. Saiand K. Onizuka, “An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators”, IEEE Journal of Solid-State Circuits, vol. 54, no. 10, pp. 2730–2742, 2019, doi: 10.1109/jssc.2019.2926649.
    • A. Sayal, S. S. T. Nibhanupudi, S. Fathimaand J. P. Kulkarni, “A 12.08-TOPS/W All-Digital Time-Domain CNN Engine Using Bi-Directional Memory Delay Lines for Energy Efficient Edge Computing”, IEEE Journal of Solid-State Circuits, vol. 55, no. 1, pp. 60–75, 2020, doi: 10.1109/jssc.2019.2939888.
    • A. Sayal, S. Fathima, S. T. Nibhanupudiand J. P. Kulkarni, “COMPAC: Compressed Time-Domain, Pooling-Aware Convolution CNN Engine With Reduced Data Movement for Energy-Efficient AI Computing”, IEEE Journal of Solid-State Circuits, vol. 56, no. 7, pp. 2205–2220, 2021, doi: 10.1109/jssc.2020.3041502.
    •  M. Yamaguchi, G. Iwamoto, Y. Nishimura, H. Tamukohand T. Morie, “An Energy-Efficient Time-Domain Analog CMOS BinaryConnect Neural Network Processor Based on a Pulse-Width Modulation Approach”, IEEE Access, vol. 9, pp. 2644–2654, 2021, doi: 10.1109/access.2020.3047619.


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