The project topics cover analog IC design including generic circuits for high frequencies, RF & mmWave transceiver block design, and digital design including VHDL programming.
Topics will be assigned to the students during our first meeting on Tuesday 27.2.
Before this, please take a look on the available topics in the list below, and consider what are your own interests. You are free to choose any topic but in case of shared interest to a certain topic, we need to negociate.
Topic: Bimodal Branch Predictor using Chisel HDLInstructor: Aleksi Korsman (aleksi.korsman@aalto,fi, room 2190)
Branch predictors are used to improve computer program performance by predicting whether a processor needs to jump to a new program location or not. In this project, the student builds a bimodal branch predictor using Chisel Hardware Description Language. So, if necessary, part of the project is for the student spending some time with tutorials to learn the basics of this language. The predictor should be verified using Chiseltest framework. The complexity of the predictor can be adjusted according to student's skills.
Topic: Direct-mapped cache using Chisel HDLInstructor: Aleksi Korsman (aleksi.korsman@aalto,fi, room 2190)
Cache is a hardware memory block that stores data so that future requests can be served faster. In this project, the student builds a direct-mapped cache controller using Chisel Hardware Description language, and a Chiseltest testbench for testing it. So, if necessary, part of the project is for the student spending time with tutorials to learn the basics of this language.
Topic: Clock data recovery implementation with VHDL or ChiselInstructor: Andrei Spelman (email@example.com, room 2189)
Clock data racovery (CDR) is used with serial datastreams to determine clock frequency of the data based on the data without passing specific/separate clock information. Preferably, this project is implemented using Chisel3 but VHDL is possible as well. Ideally, student will design CDR with Chisel, testbench with Python.
Topic: Efficient customized approximate multiplier designInstructor: Lingyun yao (firstname.lastname@example.org, room 2191)
Approximate computing is a technique that trades off some level of accuracy for improved performance, power efficiency, or other benefits. In the project student will design a digital approximate multiplier using VHDL and simulate it with VIVADO. The project will be evaluated by comparing the performance of the custom multiplier to existing solutions in terms of speed, power consumption, and/or accuracy
Topic: Efficient customized floating point multiplier designInstructor: Lingyun yao (email@example.com, room 2191)
This topic aims to design and implement a specialized floating point multiplier optimized for a specific application or use case. In the project student will design a digital approximate multiplier using VHDL and simulate it with VIVADO. The project will be evaluated by comparing the performance of the custom multiplier to existing solutions in terms of speed, power consumption, and/or accuracy.
Topic: Group work for RISC-V processor developmentInstructor: Marko Kosunen (firstname.lastname@example.org, room 2190)
Student joins a group that developes RISC-V microprosessor implementation. You will get your own sub-task. Work mode includes weekly meetings and it is MANDATORY to participate on these. If you are interested on this, keep in mind that you need to engage yourself, and be prepared for active weekly progress.
ANALOG and RF DESIGN
Topic: N-bit Thermometer Coded Vernier Delay LineInstructor: Tze Hin Cheung (Dicky) (email@example.com, room 2189)
In this topic the student implements a Vernier Delay Line which acts as a Time-to-Digital Converter. In addition to implementing the delay line, the student also charactrerizes the performance through theory and simulator.
Topic: A fractional 2/3 frequency dividerInstructor: Tze Hin Cheung (Dicky) (firstname.lastname@example.org, room 2189)
In this topic the student implements a known divide by 2/3 frequency divider operating at above 10 GHz. The student has to characterize the proper sizes for the transistor for the desired operating frequency while maintaining wide frequency operation range and low power consumption. The tasks include schematic level simulations of the design in Cadence Virtuoso and evaluation of the fractional division operation.
Topic: Mixed-signal multiplier based on R-2R laddInstructor: Omar Numan (Omar.email@example.com, room 2191)
In this topic, you will design a multiplier DAC and a Transimpedance amplifier in 45nm technology.
Topic: Flash ADC with inverter-based comparatorsInstructor: Omar Numan (Omar.firstname.lastname@example.org, room 2191)
In this topic, you will design an inverter-based comparator for a Flash ADC, some other blocks like latch and encoder for a fully working design in 45nm technology.
Topic: Ring-amplifier based multiplying D/A-converterInstructor: Santeri Porrasmaa (email@example.com, room 2189)
Analog signal processing necessitates circuit blocks such as operational amplifiers to realize mathematical operations, such as addition and substraction, on analog signals. In modern CMOS processes, the design of traditional operational amplifiers becomes increasingly difficult due to reducing intrinsic gain of the devices, lower supply voltages and unmatched reduction in transistor threshold voltages. Hence, new circuit topologies for operational amplifiers are required. In this project, the student realizes a 1.5-bit multiplying D/A-converter (MDAC) using a ring amplifier as the gain element.
Topic: Design of high-linearity sampling switchInstructor: Santeri Porrasmaa (firstname.lastname@example.org, room 2189)
In order to enable state-of-the-art performance in data converters for current and next generation communications, the sampling front-end of a data converter needs to be designed to yield sufficient performance while leaving some safety margin. A critical building block in realizing such a high-performance sampling front-end is the sample and hold circuit (S/H). In this project, the student designs a bootstrapped switch for use in an Analog-to-Digital Converter (ADC).
Topic: StrongARM latch comparatorInstructor: Miikka Tenhunen (email@example.com, room 21 86)
A comparator is a component that compares two voltages and returns a 1-bit digital value that indicates which input is larger. Comparators are often used in applications like analog-to-digital converters and different detectors. The task is to design a StrongARM comparator, a widely used architecture well known for its simplicity and efficiency. The design work includes drawing the schematic and layout and evaluating the performance through simulations.
Topic: Time to voltage converter (TVC) design for on-chip applicationsInstructor: Muhammad Tanweer (firstname.lastname@example.org, room 2191)
a. A literature review on TVC topologies. b. Comparison and selection of most suitable topology. c. Schematic design using CAD tools and perform the simulations. d. Compile and present simulation results
Topic: Coplanar capacitive sensor model design using COMSOL toolInstructor: Muhammad Tanweer (email@example.com, room 2191)
a. Literature review on coplanar capacitor designs b. Model designs using CAD tools (AutoCAD, etc) c. Importing models into COMSOL and performing calculations. d. Compile and present results
Topic: Design of a bandgap referenceInstructor: Ahmed Mohey (firstname.lastname@example.org, room 2191)
The topic includes the design of an amplifier, PTAT/CTAT Generators, and the circuitry characterization.
Topic: Design of a Low-Noise Charge AmplifierInstructor: Ahmed Mohey (email@example.com, room 2191)
The topic includes the design of an amplifier to achieve adequate gain and low noise.
Topic: Building blocks of Machine Learning acceleratorsInstructor: Kazybek Adam (firstname.lastname@example.org, room 2191)
Today machine learning (ML) accelerators are gaining great interest from both industry and research universities all around the globe. Many real-world AI problems can be solved efficiently using the ML accelerators. If you would like to start a career in this research area, then this project can be a great choice. In this project students need to build a simple neural network crossbar (10x1 is enough) containing of ideal resistors representing synapse connections (weights). The output of the network should feed an activation function circuit. Activation function circuit can be sigmoid, hyperbolic tangent, and rectified linear unit. One of them should be selected for implementation.
Topic: Analog Implementation of Softmax activation function using a neural networkInstructor: Kazybek Adam (email@example.com, room 2191)
In this project, softmax activation function is implemented in analog domain. Softmax activation function is a complex function and thereforeit iscomputationallydemanding. One part of the complexity comes from the fact that it uses exponential functions and division operation. Another part comes from the fact that it is not a regular one input and one output function, instead it takes several or more inputs and outputs“confidence levels” which add up to 1 or 100%. In this project, 10 input to 10 output softmax activation function is implemented. One interesting approach to implement it is to actually implement a neural network that was trained to implement softmax activation function.
Topic: Design and model a Vector Matrix Multiplier (VMM) circuit using ideal componentsInstructor: Gaurav Singh (firstname.lastname@example.org, room 2191)
VMM circuits are used for performing In Memory Computations (IMC), which are very popular in Hardware Accelerators for AI Applications. These accelerators are very power efficient in doing AI Inferences using analog processing instead of doing it conventionally in the digital domain.