Please note! Course description is confirmed for two academic years, which means that in general, e.g. Learning outcomes, assessment methods and key content stays unchanged. However, via course syllabus, it is possible to specify or change the course execution in each realization of the course, such as how the contact sessions are organized, assessment methods weighted or materials used.
Is familiar with the VHDL-hardware description language and the digital design implementation flow (synthesis tools) from VHDL to layout. Is familiar with the functionality of microcontrollers and basics of programming with assembly language.
Schedule: 25.02.2019 - 27.05.2019
Teacher in charge (valid 01.08.2020-31.07.2022): Marko Kosunen, Kari Stadius
Teacher in charge (applies in this implementation): Marko Kosunen, Kari Stadius
Contact information for the course (applies in this implementation):
CEFR level (applies in this implementation):
Language of instruction and studies (valid 01.08.2020-31.07.2022):
Teaching language: English
Languages of study attainment: English
CONTENT, ASSESSMENT AND WORKLOAD
Six coding exercises that teach the elementary structures of VHDL and simulation methods. Self -guided design project about VHDL description of a microcontroller and its synthesis to layout with digital synthesis and place-and-route-tools.
Assessment Methods and Criteria
Passed VHDL-coding exercises and study diary of the design project.
Introductory lectures (2h, 2 times)
VHDL-coding exercises (2h, 6 times)
Microcontroller implementation with VHDL as self-paced project 110h. Possibility for guidance in weekly exercise hours (2h per week).
Handouts, P. Ashenden, "Designers guide to VHDL", Third edition, Elsevier, 2008.
Substitutes for Courses
S-87.3186 and S-87.3187
- Teacher: Tze Cheung
- Teacher: Ilia Kempi
- Teacher: Marko Kosunen
- Teacher: Kari Stadius
- Teacher: Vishnu Unnikrishnan