Please note! Course description is confirmed for two academic years, which means that in general, e.g. Learning outcomes, assessment methods and key content stays unchanged. However, via course syllabus, it is possible to specify or change the course execution in each realization of the course, such as how the contact sessions are organized, assessment methods weighted or materials used.


Student gets acquainted with the history of digital microelectronics, elementary building blocks (logic gates), and is familiar with the electrical functionality of the gates and the most important electrical relationships affecting the functionality.  Student is familiar with the most common methods for power consumption and delay optimization. He also knows the most common arithmetic building blocks, understand their functionality, and  is familiar with the  optimization methods used for adders and multipliers.  Student is familiarized with the commonly used power/speed trade-off methods on algorithmic level, and is familiar with the commonly used  advanced algorithms, and understand what the algorithm optimization is based on.

Credits: 5

Schedule: 10.01.2022 - 24.02.2022

Teacher in charge (valid for whole curriculum period):

Teacher in charge (applies in this implementation): Marko Kosunen, Kari Stadius

Contact information for the course (applies in this implementation):

CEFR level (valid for whole curriculum period):

Language of instruction and studies (applies in this implementation):

Teaching language: English. Languages of study attainment: English


  • valid for whole curriculum period:

    Introduction (history of digital microelectronics), Inverter, Logic, Synchronization circuits, Bit transfer and signaling, elementary arithmetic building blocks, algorithm level optimization methods.

Assessment Methods and Criteria
  • valid for whole curriculum period:

    Exercises 30%, Presentation 20%, design project 20%, Exam 30%. 50% of exam points are required to qualify.

  • valid for whole curriculum period:

    Lecture 14h  (2h, 7 times): Introduction to theory and motivation.

    Exercises (2h, 7 times) Mathematical handling of the topic and design methods.

    Presentation  (preparations 6h) and listening the presentations of the others  (4h).

    Design project  ca. 10h.

    Exam 2h.

    Independent work ca. 60h


Study Material
  • valid for whole curriculum period:

    Lecture slides

    Rabaey, Chandrakasan, Nikolic, "Digital Integrated Circuits- A design perspective", Prentice Hall 2003.

    Parhi, "VLSI Digital Signal Processing Systems-design and implementation", Wiley 1999.

Substitutes for Courses


Further Information
  • valid for whole curriculum period:

    Teaching Period:

    2020-2021 Spring III

    2021-2022 Spring III

    Course Homepage:

    Registration for Courses: In the academic year 2021-2022, registration for courses will take place on Sisu ( instead of WebOodi.