LEARNING OUTCOMES
After this course you will know how to use Verilog hardware description language (HDL) to develop digital systems. You will know Verilog development workflow for FPGA, including what components FPGA toolchain contains. You will know how to implement digital protocols for communication inside and outside of FPGA.
Credits: 5
Schedule: 08.01.2025 - 28.05.2025
Teacher in charge (valid for whole curriculum period):
Teacher in charge (applies in this implementation): Kalle Ruttik
Contact information for the course (applies in this implementation):
CEFR level (valid for whole curriculum period):
Language of instruction and studies (applies in this implementation):
Teaching language: English. Languages of study attainment: English
CONTENT, ASSESSMENT AND WORKLOAD
Content
valid for whole curriculum period:
During the course you will develop, simulate and test Verilog designs. Participants implement common digital protocols for communication inside and outside of a FPGA. The protocols are implemented and tested on physical hardware.
Assessment Methods and Criteria
valid for whole curriculum period:
Exercises and laboratory works
Workload
valid for whole curriculum period:
Lectures, exercises, laboratory work.
DETAILS
Substitutes for Courses
valid for whole curriculum period:
Prerequisites
valid for whole curriculum period:
FURTHER INFORMATION
Further Information
valid for whole curriculum period:
Teaching Language: English
Teaching Period: 2024-2025 Spring III - IV
2025-2026 Spring III - IVRegistration:
Max number limited. Priority in order: Computer Engineering BSc major students, Communication Engineering Msc students & Information Technology Bsc students.